[ DevCourseWeb.com ] Udemy - Learn Vivado from Top to Bottom - Your Complete Guide

Creation Time	April 16, 2024, 2:53 p.m.
Last Access Time	Nov. 24, 2024, 4:48 a.m.
File Size	938.0 MB
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~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/005 Step 4 - Add Existing Custom IP.mp4 48.8 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/001 Project Design Flow Walkthrough.mp4 37.1 MB
~Get Your Files Here !/07 - Automating Vivado/001 TCL Script Introduction.mp4 31.1 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/005 Vivado Debugging Tools Introduction.mp4 30.6 MB
~Get Your Files Here !/10 - High Level Synthesis Tool/001 High Level Synthesis Tool Introduction.mp4 29.6 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/006 How to Use the Integrated Logic Analyzer (ILA) Core for Debugging.mp4 27.0 MB
~Get Your Files Here !/01 - Introduction/001 Welcome to the Course.mp4 25.1 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/007 How to Use the Virtual IO (VIO) Core for Debugging.mp4 23.4 MB
~Get Your Files Here !/01 - Introduction/003 Vivado Download and Installation.mp4 22.1 MB
~Get Your Files Here !/05 - IP Core Design Examples/002 Xilinx Memory Interface Generator (MIG) IP Core.mp4 21.9 MB
~Get Your Files Here !/01 - Introduction/002 Introduction to the Vivado Tool Suite.mp4 21.7 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/004 Create IP Cores from a Block Design.mp4 21.6 MB
~Get Your Files Here !/03 - Pin Planning Tool/001 IO Pin Planning Tool Introduction.mp4 21.0 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/008 Create an AXI IP Core Peripheral Step 3.mp4 21.0 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/003 Create IP Cores from a Specific Directory.mp4 20.2 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/003 Modifying the Simulation Waveform.mp4 19.9 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/006 Step 5 - Add Create Design Constraints.mp4 19.8 MB
~Get Your Files Here !/02 - Vivado Basics/008 Working with Block Designs in Vivado.mp4 18.9 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/007 Step 6 - Simulate and Verify Design.mp4 18.7 MB
~Get Your Files Here !/09 - Working with Soft Core Processors/002 Add AXI Peripherals to Your MicroBlaze Processor.mp4 18.2 MB
~Get Your Files Here !/03 - Pin Planning Tool/003 Create and Place IO Ports.mp4 16.0 MB
~Get Your Files Here !/09 - Working with Soft Core Processors/001 Creating Your First Softcore Processor Project.mp4 15.9 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/014 Managing a Custom IP Core Repository.mp4 14.8 MB
~Get Your Files Here !/03 - Pin Planning Tool/006 Generate Contraints File and Top Level HDL File.mp4 14.7 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/blk_mem_gen_v8_3/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd 14.1 MB
~Get Your Files Here !/05 - IP Core Design Examples/001 Configure Internal FPGA Block RAM (BRAM).mp4 13.8 MB
~Get Your Files Here !/02 - Vivado Basics/005 Vivado Example Project.mp4 13.7 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/002 Simulating Your Designs in Vivado.mp4 13.2 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/012 Adding IP Cores to Your Repository.mp4 13.0 MB
~Get Your Files Here !/02 - Vivado Basics/007 Creating New Files.mp4 12.8 MB
~Get Your Files Here !/05 - IP Core Design Examples/004 Using Vivado's Connection Automation and Regerating Block Design Layouts.mp4 12.5 MB
~Get Your Files Here !/02 - Vivado Basics/003 Importing a Xilinx ISE Project Into Vivado.mp4 12.1 MB
~Get Your Files Here !/02 - Vivado Basics/009 Generating the FPGA Configuration File.mp4 11.7 MB
~Get Your Files Here !/06 - Working with Design Constraints/003 Creating Clock Constraints.mp4 11.3 MB
~Get Your Files Here !/07 - Automating Vivado/005 How to Create Your Own Custom TCL Scripts.mp4 11.2 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/004 Forcing Signal Values for Simulation.mp4 11.1 MB
~Get Your Files Here !/07 - Automating Vivado/004 Using TCL Scripts in Your Custom IP Core.mp4 10.8 MB
~Get Your Files Here !/07 - Automating Vivado/002 Build a Vivado Project Using TCL Scripts.mp4 10.5 MB
~Get Your Files Here !/03 - Pin Planning Tool/005 Report Simultaneous Switching Noise SSN.mp4 10.3 MB
~Get Your Files Here !/06 - Working with Design Constraints/002 Applying IO Constraints.mp4 10.1 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/009 Customizing IP Cores.mp4 10.0 MB
~Get Your Files Here !/13 - Conclusion/001 Conclusion.mp4 10.0 MB
~Get Your Files Here !/05 - IP Core Design Examples/003 Connecting Multiple AXI Peripherals to a Single Master.mp4 9.9 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/008 Step 7 - Generate the FPGA Configuration File.mp4 9.8 MB
~Get Your Files Here !/02 - Vivado Basics/006 Add Existing Files to a Project.mp4 9.7 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/009 Step 8 – Program your Board to Verify Functionality.mp4 9.2 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/006 Create an AXI IP Core Peripheral Step 1.mp4 9.1 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/002 Using IP Cores.mp4 9.0 MB
~Get Your Files Here !/02 - Vivado Basics/004 Create a Project From a Predefined Template.mp4 8.2 MB
~Get Your Files Here !/11 - Programming the FPGA/003 Loading the Configuration File on the FPGA.mp4 7.6 MB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/004 Step 3 - Create Project in Vivado.mp4 7.5 MB
~Get Your Files Here !/02 - Vivado Basics/002 Creating a New Project in Vivado.mp4 7.4 MB
~Get Your Files Here !/03 - Pin Planning Tool/002 Create an IO Pin Planning Project.mp4 7.2 MB
~Get Your Files Here !/02 - Vivado Basics/010 Programming Your Development Board.mp4 7.2 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/Simulation_Example_sim_behav.wdb 7.2 MB
~Get Your Files Here !/02 - Vivado Basics/001 Opening Vivado.mp4 6.8 MB
~Get Your Files Here !/02 - Vivado Basics/011 Documentation Navigator.mp4 6.5 MB
~Get Your Files Here !/03 - Pin Planning Tool/004 Perform a Design Rules Check.mp4 6.3 MB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/013 Adding a Custom IP Core Repository to a Vivado Project.mp4 6.2 MB
~Get Your Files Here !/07 - Automating Vivado/003 Populate a Block Design Using TCL Scripts.mp4 4.9 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xml 4.5 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0_vhsyn_rfs.vhd 2.1 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.bit 2.1 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_routed.dcp 1.3 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_placed.dcp 1.1 MB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_localparam_inc.v 932.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_opt.dcp 918.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx 731.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.dcp 580.9 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg/BASYS_7_seg_documentation.pdf 560.2 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/doc/BASYS_7_seg_documentation.pdf 560.2 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/doc/BASYS_7_seg_documentation.pdf 560.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xci 447.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/synth/design_1_ila_0_0.vhd 409.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_addsub_v12_0/hdl/c_addsub_v12_0_vh_rfs.vhd 383.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_addsub_v12_0/hdl/c_addsub_v12_0_vh_rfs.vhd 383.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt 352.2 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/002 Project-Requirements.pdf 338.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.pb 302.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/usage_statistics_webtalk.xml 301.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/ila_v6_0_syn_rfs.v 260.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/hw_1/layout/hw_ila_1.layout 241.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh 236.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/ip/46a4281943398b66/dbg_hub_CV.dcp 221.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_utils_v3_0_5/xbip_utils_v3_0_5_pkg.vdb 214.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.log 207.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper.vds 206.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/usage_statistics_webtalk.html 197.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsimk.exe 187.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_xsdbm.v 171.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/xsdbm_v1_1_vl_rfs.v 166.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0_vh_rfs.vhd 155.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0_vh_rfs.vhd 155.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd 154.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd 154.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_param_inc.v 144.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 139.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd 139.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_counter_v3_0/hdl/xbip_counter_v3_0_vh_rfs.vhd 127.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_counter_v3_0/hdl/xbip_counter_v3_0_vh_rfs.vhd 127.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0_vh_rfs.vhd 125.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0_vh_rfs.vhd 125.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/pkg_gate_bit_v12_0.vdb 120.0 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_isim_beh.exe 117.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0.vhd 88.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/ltlib_v1_0_vl_rfs.v 87.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 84.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd 84.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.xml 77.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.sysdef 75.5 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.bit 71.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_base_legacy.vdb 70.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_lut6_legacy.vdb 69.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_pkg_legacy.vdb 68.7 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ibs 60.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_io_placed.rpt 60.1 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_par.xrpt 59.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_in_ports_inc.v 59.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_legacy.vdb 59.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_legacy.vdb 56.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_pkg.vdb 54.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_control_sets_placed.rpt 53.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_pkg.vdb 48.9 KB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/MouseCtl.vhd 47.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_pkg.vdb 43.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_viv.vdb 41.5 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/component.xml 39.6 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/component.xml 39.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_viv.vdb 37.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbs_v1_0/hdl/xsdbs_v1_0_vl_rfs.v 36.3 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/usage_statistics_webtalk.html 35.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48_wrapper_v3_0_4_pkg.vdb 34.3 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xise 32.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_viv.vdb 32.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0_vh_rfs.vhd 31.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0_vh_rfs.vhd 31.9 KB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/Ps2Interface.vhd 31.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_power_routed.rpt 30.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_pkg.vdb 30.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48e2_wrapper_v3_0.vdb 29.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48e1_wrapper_v3_0.vdb 27.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd 26.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_vh_rfs.vhd 26.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.vdi 26.6 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_pad.txt 26.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/runme.log 26.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48e_wrapper_v3_0.vdb 25.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper.hwdef 25.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hdl/design_1.hwdef 25.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/fabric_counter.vdb 24.7 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/007 Creating an AXI IP Core Peripheral - Step 2.html 24.6 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_addsub_v12_0/hdl/c_addsub_v12_0.vhd 12.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_addsub_v12_0/hdl/c_addsub_v12_0.vhd 12.3 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.xrpt 12.3 KB
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~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/binary_bcd/component.xml 12.1 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_viv.vdb 11.7 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/006 How to Use the Integrated Logic Analyzer (ILA) Core for Debugging_en.srt 11.3 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_xst.xrpt 11.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_ver_inc.v 10.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0.vhd 10.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_gate_bit_v12_0/hdl/c_gate_bit_v12_0.vhd 10.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.xci 10.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0.vhd 10.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_counter_binary_v12_0/hdl/c_counter_binary_v12_0.vhd 10.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd 10.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd 10.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_utilization_placed.rpt 10.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_viv.vdb 10.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/route_design.pb 10.4 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.xci 10.3 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/usage_statistics_ext_labtool.html 10.3 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.syr 10.2 KB
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~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/PWM/component.xml 10.0 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/src/basys_image.PNG 9.9 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/007 How to Use the Virtual IO (VIO) Core for Debugging_en.srt 9.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_counter_v3_0/hdl/xbip_counter_v3_0.vhd 9.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_counter_v3_0/hdl/xbip_counter_v3_0.vhd 9.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/compile.log 9.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xvhdl.log 9.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd 9.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0.vhd 9.4 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/003 Create IP Cores from a Specific Directory_en.srt 9.3 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/001 Introduction to IP Cores.html 9.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt 9.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/003 Modifying the Simulation Waveform_en.srt 9.1 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd 8.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd 8.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.xpr 8.8 KB
~Get Your Files Here !/01 - Introduction/003 Vivado Download and Installation_en.srt 8.7 KB
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~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_summary.html 8.6 KB
~Get Your Files Here !/05 - IP Core Design Examples/002 Xilinx Memory Interface Generator (MIG) IP Core_en.srt 8.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.reloc 8.4 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/design.tcl 8.3 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/debug_hw_design/design.tcl 8.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8.vdb 8.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xelab.pb 8.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/ipstatic/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd 8.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd 8.1 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/008 Create an AXI IP Core Peripheral Step 3_en.srt 8.1 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.xdbg 7.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ila_v6_0/hdl/verilog/ila_v6_0_1_ila_lib_function.v 7.7 KB
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~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/bd/bd.tcl 7.7 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/004 Create IP Cores from a Block Design_en.srt 7.6 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/verilog/ltlib_v1_0_0_lib_function.v 7.5 KB
~Get Your Files Here !/02 - Vivado Basics/008 Working with Block Designs in Vivado_en.srt 7.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1.vdb 7.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_1_inc.v 7.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbs_v1_0/hdl/verilog/xsdbs_v1_0_2_inc.v 7.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_c_counter_binary_0_0.vdb 7.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/ltlib_v1_0/hdl/verilog/ltlib_v1_0_0_ver_inc.v 7.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8.vdb 7.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/hdl/design_1.vhd 7.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1.vdb 7.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/ISEWrap.js 7.1 KB
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~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/clk_wiz_0_clk_wiz.vhd 7.1 KB
~Get Your Files Here !/09 - Working with Soft Core Processors/001 Creating Your First Softcore Processor Project_en.srt 7.0 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/BASYS_7_seg_AXI_v1_0_tb.v 6.8 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/BASYS_7_seg_AXI_v1_0_tb.v 6.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/hdl/design_1.vhd 6.8 KB
~Get Your Files Here !/09 - Working with Soft Core Processors/002 Add AXI Peripherals to Your MicroBlaze Processor_en.srt 6.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/001 Creating Simulation Files (Test Benches).html 6.8 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/007 Step 6 - Simulate and Verify Design_en.srt 6.7 KB
~Get Your Files Here !/07 - Automating Vivado/design_1_tcl/design_1.tcl 6.6 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_dsp48_addsub_v3_0_1/xbip_dsp48_addsub_v3_0_1_viv_comp.vdb 5.7 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_addsub_v12_0_8/c_addsub_v12_0_8_viv_comp.vdb 5.5 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/014 Managing a Custom IP Core Repository_en.srt 5.5 KB
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~Get Your Files Here !/03 - Pin Planning Tool/006 Generate Contraints File and Top Level HDL File_en.srt 5.4 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_ngdbuild.xrpt 5.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1.vdb 5.4 KB
~Get Your Files Here !/05 - IP Core Design Examples/001 Configure Internal FPGA Block RAM (BRAM)_en.srt 5.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/basys_7_seg.vdb 5.3 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1.vdb 5.2 KB
~Get Your Files Here !/01 - Introduction/004 Supported FPGAs and Development Boards.html 5.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_c_counter_binary_0_0/sim/design_1_c_counter_binary_0_0.vhd 5.1 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xsdbm_v1_1/hdl/verilog/xsdbm_v1_1_1_icon_inc.v 5.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1.vdb 4.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/doc/c_counter_binary_v12_0_changelog.txt 4.9 KB
~Get Your Files Here !/02 - Vivado Basics/009 Generating the FPGA Configuration File_en.srt 4.8 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/001 Project Design Flow Walkthrough_en.srt 4.8 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.bgn 4.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/004 Forcing Signal Values for Simulation_en.srt 4.7 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/planAhead.log 4.7 KB
~Get Your Files Here !/02 - Vivado Basics/003 Importing a Xilinx ISE Project Into Vivado_en.srt 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/elaborate.log 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_viv_comp.vdb 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/002 Simulating Your Designs in Vivado_en.srt 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_counter_binary_v12_0_8/c_counter_binary_v12_0_8_comp.vdb 4.7 KB
~Get Your Files Here !/07 - Automating Vivado/005 How to Create Your Own Custom TCL Scripts_en.srt 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci 4.7 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/design_1_xlslice_2_0.xci 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/design_1_xlslice_3_0.xci 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.xci 4.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/synth/design_1_BASYS_7_seg_0_0.vhd 4.6 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_map.ngm 4.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_viv_comp.vdb 4.5 KB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/UART_TX_CTRL.vhd 4.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_gate_bit_v12_0_1/c_gate_bit_v12_0_1_comp.vdb 4.5 KB
~Get Your Files Here !/03 - Pin Planning Tool/005 Report Simultaneous Switching Noise SSN_en.srt 4.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/Simulation_Example_sim_vhdl.prj 4.4 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/012 Adding IP Cores to Your Repository_en.srt 4.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/doc/ila_v6_0_changelog.txt 4.3 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0.vhd 4.3 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/hdl/BASYS_7_seg_AXI_v1_0.vhd 4.3 KB
~Get Your Files Here !/05 - IP Core Design Examples/004 Using Vivado's Connection Automation and Regerating Block Design Layouts_en.srt 4.3 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1.hwdef 4.3 KB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/clk_wiz_0.vhd 4.2 KB
~Get Your Files Here !/07 - Automating Vivado/002 Build a Vivado Project Using TCL Scripts_en.srt 4.1 KB
~Get Your Files Here !/07 - Automating Vivado/001 TCL Script Introduction_en.srt 4.1 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/009 Step 8 – Program your Board to Verify Functionality_en.srt 4.1 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_routed.rpt 4.1 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/xgui/BASYS_7_seg_AXI_v1_0.tcl 4.0 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/xgui/BASYS_7_seg_AXI_v1_0.tcl 4.0 KB
~Get Your Files Here !/06 - Working with Design Constraints/003 Creating Clock Constraints_en.srt 4.0 KB
~Get Your Files Here !/07 - Automating Vivado/004 Using TCL Scripts in Your Custom IP Core_en.srt 4.0 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_BASYS_7_seg_0_0/sim/design_1_BASYS_7_seg_0_0.vhd 3.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/sim/design_1_BASYS_7_seg_0_0.vhd 3.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_viv_comp.vdb 3.9 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/002 Using IP Cores_en.srt 3.9 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_counter_v3_0_1/xbip_counter_v3_0_1_comp.vdb 3.9 KB
~Get Your Files Here !/02 - Vivado Basics/001 Opening Vivado_en.srt 3.9 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/design.tcl 3.8 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/example_designs/bfm_design/design.tcl 3.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/project.wdf 3.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/project.wdf 3.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_0_0/synth/design_1_xlslice_0_0.vhd 3.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_1_0/synth/design_1_xlslice_1_0.vhd 3.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_2_0/synth/design_1_xlslice_2_0.vhd 3.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_xlslice_3_0/synth/design_1_xlslice_3_0.vhd 3.8 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/simulation_example_sim.vdb 3.8 KB
~Get Your Files Here !/02 - Vivado Basics/006 Add Existing Files to a Project_en.srt 3.7 KB
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/create_project.tcl 3.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1_viv_comp.vdb 3.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/synthesis.wdf 3.7 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/c_reg_fd_v12_0_1/c_reg_fd_v12_0_1_comp.vdb 3.7 KB
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_isim_beh.wdb 3.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/synth/design_1_Hex_to_7_Seg_0_0.vhd 3.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/synth/design_1_Hex_to_7_Seg_1_0.vhd 3.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/synth/design_1_Hex_to_7_Seg_2_0.vhd 3.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/synth/design_1_Hex_to_7_Seg_3_0.vhd 3.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/005 Vivado Debugging Tools Introduction_en.srt 3.6 KB
~Get Your Files Here !/10 - High Level Synthesis Tool/001 High Level Synthesis Tool Introduction_en.srt 3.6 KB
~Get Your Files Here !/06 - Working with Design Constraints/002 Applying IO Constraints_en.srt 3.6 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.vho 3.5 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/008 Step 7 - Generate the FPGA Configuration File_en.srt 3.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_viv_comp.vdb 3.5 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg/BASYS_7_seg.vhd 3.5 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/src/BASYS_7_seg.vhd 3.5 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg/BASYS_7_seg.vhd 3.5 KB
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/src/BASYS_7_seg.vhd 3.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ipshared/xilinx.com/basys_7_seg_v1_0/BASYS_7_seg.vhd 3.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ipshared/xilinx.com/basys_7_seg_v1_0/BASYS_7_seg.vhd 3.5 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/BASYS_7_seg/BASYS_7_seg.vhd 3.5 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_addsub_v3_0_1/xbip_addsub_v3_0_1_comp.vdb 3.5 KB
~Get Your Files Here !/11 - Programming the FPGA/003 Loading the Configuration File on the FPGA_en.srt 3.4 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/design_1_wrapper.vdb 3.3 KB
~Get Your Files Here !/07 - Automating Vivado/GPIO/src/hdl/debouncer.vhd 3.3 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.xci 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.xci 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.xci 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.xci 3.2 KB
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/binary_bcd/binary_bcd.vhd 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_BASYS_7_seg_0_0/design_1_BASYS_7_seg_0_0.veo 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xil_defaultlib/hex_to_7_seg.vdb 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_viv_comp.vdb 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_c_counter_binary_0_0/design_1_c_counter_binary_0_0.vho 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/webtalk/usage_statistics_ext_xsim.html 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/xbip_pipe_v3_0_1/xbip_pipe_v3_0_1_comp.vdb 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/design_1_Hex_to_7_Seg_0_0.vho 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_1_0/design_1_Hex_to_7_Seg_1_0.vho 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_2_0/design_1_Hex_to_7_Seg_2_0.vho 3.2 KB
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_Hex_to_7_Seg_3_0/design_1_Hex_to_7_Seg_3_0.vho 3.2 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/bd/design_1/ip/design_1_Hex_to_7_Seg_0_0/sim/design_1_Hex_to_7_Seg_0_0.vhd 3.0 KB
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~Get Your Files Here !/04 - Intellectual Property (IP) Cores/009 Customizing IP Cores_en.srt 2.9 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/gen_run.xml 2.8 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.vhd 2.6 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.sh 1.2 KB
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~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_power_summary_routed.pb 674 bytes
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/_READ_ME_.txt 670 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_route_status.rpt 651 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pa.fromHdl.tcl 646 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_fpga_editor.log 645 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/xst.xmsgs 625 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/elaborate.bat 615 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/src/design_1_ooc.xdc 600 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/bd/design_1/design_1_ooc.xdc 600 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/ibiswriter.xmsgs 589 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/fileset.xml 589 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/constrs_1/fileset.xml 561 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/sources_1/fileset.xml 547 bytes
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/cleanup.sh 533 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/xdl.xmsgs 512 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/Makefile 484 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/Makefile 484 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/Compile_Options.txt 467 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/external-assets-links.txt 464 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/Simulation_Example_sim.tcl 458 bytes
~Get Your Files Here !/07 - Automating Vivado/GPIO/proj/cleanup.cmd 453 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.pcf 451 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/hdpdeps.ref 423 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/java_command_handlers.wdf 417 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead.ngc2edif.log 413 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_summary.xml 408 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/labtool_webtalk.log 406 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/htr.txt 401 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/htr.txt 393 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ut 392 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/runs/impl_1.psg 391 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/labtool_webtalk.log 386 bytes
~Get Your Files Here !/Bonus Resources.txt 386 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/bitgen.xmsgs 367 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_xmsgs/ngdbuild.xmsgs 367 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/constrs_1/designprops.xml 365 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/constrs_1/fileset.xml 361 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsimkernel.log 360 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado.begin.rst 352 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/compile.bat 345 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/Simulation_Example.lpr 343 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.rtti 332 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/external-assets-links.txt 324 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/simulate.bat 321 bytes
~Get Your Files Here !/06 - Working with Design Constraints/external-assets-links.txt 313 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_bitgen.xwbt 306 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.ppr 277 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/xsim.wdf 256 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/ports.xml 253 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_11.xml 251 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_5.xml 251 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_8.xml 251 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_utilization_placed.pb 249 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/design_1_wrapper_utilization_synth.pb 249 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_10.xml 244 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_2.xml 244 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_4.xml 244 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_7.xml 244 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.ppr 238 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xst/work/hdllib.ref 232 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_1.xml 230 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_3.xml 230 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_6.xml 230 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/jobs/vrs_config_9.xml 230 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/runme.bat 229 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/runme.bat 229 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.mdd 210 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.mdd 210 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/design_1/xgui/design_1_v1_0.tcl 205 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.srcs/sources_1/imports/Hex_to_7_Seg/xgui/Hex_to_7_Seg_v1_0.tcl 205 bytes
~Get Your Files Here !/12 - Project Design Flow Example Using Vivado/Final_Project/ip_repo/Hex_to_7_Seg/xgui/Hex_to_7_Seg_v1_0.tcl 205 bytes
~Get Your Files Here !/01 - Introduction/external-assets-links.txt 197 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/full_adder_2.drc 197 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.c 194 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/src/BASYS_7_seg_AXI.c 194 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_1/Full_Adder_2.data/runs/runs.xml 190 bytes
Get Bonus Downloads Here.url 182 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.tcl 177 bytes
~Get Your Files Here !/04 - Intellectual Property (IP) Cores/Custom_IP_Cores/BASYS_7_seg_AXI_1.0/drivers/BASYS_7_seg_AXI_v1_0/data/BASYS_7_seg_AXI.tcl 177 bytes
~Get Your Files Here !/07 - Automating Vivado/external-assets-links.txt 177 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/init_design.begin.rst 177 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/opt_design.begin.rst 177 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/place_design.begin.rst 177 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/route_design.begin.rst 177 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/write_bitstream.begin.rst 177 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.begin.rst 175 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.unroutes 156 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.ucf 153 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado.pb 149 bytes
~Get Your Files Here !/03 - Pin Planning Tool/external-assets-links.txt 143 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.ip_user_files/README.txt 130 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/project.wpc 121 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/sources_1/chipscope.xml 113 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.cache/wt/synthesis_details.wdf 100 bytes
~Get Your Files Here !/05 - IP Core Design Examples/external-assets-links.txt 95 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/_ngo/netlist.lst 84 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_vhdl.prj 81 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/planAhead_run_4/Full_Adder_2.data/constrs_1/usercols.xml 78 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/test_Full_Adder_2_stx_beh.prj 75 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/test_Full_Adder_2_beh.prj 65 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/webtalk/xsim_webtallk.info 64 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.hw/webtalk/xsim_webtallk.info 59 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.tmp/edit_ip_project.hw/webtalk/xsim_webtallk.info 59 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/simulate.log 50 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.xpi 46 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/isim.cmd 44 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_route_status.pb 44 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/design_1_wrapper_drc_routed.pb 37 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2_stx_beh.prj 35 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.prj 30 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/TempBreakPointFile.txt 29 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/pepExtractor.prj 25 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/xilinxsim.ini 16 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsim.svtype 8 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.lso 6 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/Full_Adder_2.stx 0 bytes
~Get Your Files Here !/02 - Vivado Basics/Full_Adder_2/compxlib.log 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/Vivado_Implementation.queue.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/init_design.end.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/opt_design.end.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/place_design.end.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/route_design.end.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/vivado.end.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/impl_1/write_bitstream.end.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/Vivado_Synthesis.queue.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.runs/synth_1/vivado.end.rst 0 bytes
~Get Your Files Here !/08 - Hardware Design Debugging and Verification/Simulation_Example/Simulation_Example.sim/sim_1/behav/xsim.dir/Simulation_Example_sim_behav/xsimcrash.log 0 bytes

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