RavindraBabu Ravula - GATE - 2021 - Computer Organization and Architecture - CoursesGhar

Creation Time	Aug. 5, 2024, 12:06 a.m.
Last Access Time	Aug. 12, 2024, 2:39 p.m.
File Size	9.2 GB
Keywords	and CoursesGhar - Architecture Computer 2021 Organization GATE RavindraBabu Ravula
Total Requests	3
Total Files	163
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5.ALU Data path and Control Unit/9.Decode phase and instruction types.mp4 318.1 MB
6.IO interface/10.DMA - 1.mp4 242.2 MB
5.ALU Data path and Control Unit/16.Execute phase of IO related instructions.mp4 203.8 MB
7.Pipelining/1.Introduction to pipelining.m4v 202.5 MB
6.IO interface/9.Interrupt overhead.mp4 197.1 MB
5.ALU Data path and Control Unit/18.Implementing Interrupts.mp4 187.8 MB
5.ALU Data path and Control Unit/22.Microprogrammed control unit - 2.mp4 157.2 MB
4.Machine instructions and Addressing modes/24.Interrupts.mp4 150.8 MB
1.Cache/2.Direct mapping.mkv 150.5 MB
6.IO interface/4.Synchronous vs asynchronous transmission Page.mp4 134.1 MB
5.ALU Data path and Control Unit/1.Introduction.mp4 128.8 MB
7.Pipelining/16.GATE 2000 question.mp4 127.4 MB
1.Cache/18.Gate 2006 question on Hit Latency.mp4 126.0 MB
4.Machine instructions and Addressing modes/21.Numerical example on flags.mp4 124.5 MB
6.IO interface/5.Modes of IO transfer Page.mp4 121.3 MB
5.ALU Data path and Control Unit/4.Connecting all the units.mp4 118.4 MB
6.IO interface/8.Parallel connection.mp4 116.2 MB
1.Cache/10.Problems on set associative mapping.mkv 113.6 MB
7.Pipelining/18.Branch prediction and speculative execution.mp4 111.5 MB
7.Pipelining/21.Data Hazards.mp4 107.8 MB
5.ALU Data path and Control Unit/21.Microprogrammed control unit - 1.mp4 105.4 MB
1.Cache/8.Numericals on associative associative.mkv 103.9 MB
4.Machine instructions and Addressing modes/20.Flags.mp4 101.6 MB
5.ALU Data path and Control Unit/17.Interrupt driven IO Page.mp4 99.2 MB
4.Machine instructions and Addressing modes/2.Computer organisations based on Registers.m4v 99.0 MB
4.Machine instructions and Addressing modes/18.Shift instructions.mp4 94.6 MB
4.Machine instructions and Addressing modes/23.Call and return.mp4 94.1 MB
7.Pipelining/12.Control dependency - 1.mp4 94.0 MB
4.Machine instructions and Addressing modes/25.RISC and CISC.mp4 92.8 MB
6.IO interface/1.Introduction Page.m4v 90.6 MB
5.ALU Data path and Control Unit/2.Bus using multiplexers.mp4 90.6 MB
2.Memory Interfacing/10.Example 4.mp4 90.4 MB
6.IO interface/6.Priority based interrupt system.mp4 88.6 MB
7.Pipelining/11.Structural dependency - 2.mp4 86.6 MB
7.Pipelining/5.Pipeline example.mp4 84.8 MB
5.ALU Data path and Control Unit/10.Compute EA phase.mp4 84.4 MB
7.Pipelining/13.Control dependency - 2.mp4 84.3 MB
7.Pipelining/14.Control dependency - 3.mp4 83.6 MB
5.ALU Data path and Control Unit/11.Execute phase of memory reference instructions-1.mp4 80.5 MB
5.ALU Data path and Control Unit/12.Execute phase of memory reference instructions-2.mp4 80.3 MB
1.Cache/5.Direct mapping Hardware implementation.mkv 80.2 MB
7.Pipelining/23.GATE 2010 question.mp4 78.1 MB
1.Cache/1.Introduction to cache memory.mkv 74.5 MB
4.Machine instructions and Addressing modes/3.Addressing modes.m4v 74.0 MB
4.Machine instructions and Addressing modes/1.Introduction.m4v 73.9 MB
4.Machine instructions and Addressing modes/5.Register Mode and Register Indirect mode.mp4 73.5 MB
4.Machine instructions and Addressing modes/19.Program control instructions.mp4 73.1 MB
1.Cache/13.Gate 95 99 01 and 07 Questions.m4v 71.7 MB
7.Pipelining/25.Gate 2015 question on Pipeline.mp4 70.2 MB
1.Cache/21.Gate 2014 question on Cache Size.mp4 69.4 MB
7.Pipelining/22.Operand forwarding.mp4 68.9 MB
6.IO interface/11.DMA - 2.mp4 68.6 MB
2.Memory Interfacing/13.Example 7.mp4 67.2 MB
5.ALU Data path and Control Unit/13.Execute phase of memory reference instructions-3.mp4 65.4 MB
5.ALU Data path and Control Unit/14.Execute phase of memory reference instructions-4.mp4 65.2 MB
6.IO interface/14.Gate question 3.mp4 64.4 MB
5.ALU Data path and Control Unit/19.Hardwired control unit ex - 1.mp4 63.2 MB
1.Cache/3.Direct mapping problems.mkv 62.6 MB
5.ALU Data path and Control Unit/8.Fetch phase.mp4 62.5 MB
5.ALU Data path and Control Unit/3.Units of a CPU.mp4 61.8 MB
7.Pipelining/17.GATE 2014 question.mp4 61.5 MB
6.IO interface/7.Daisy chain or serial connection.mp4 60.9 MB
5.ALU Data path and Control Unit/5.Timing circuit.mp4 58.2 MB
7.Pipelining/15.GATE 2006 question.mp4 58.1 MB
2.Memory Interfacing/3.2 Level memory.m4v 58.0 MB
4.Machine instructions and Addressing modes/17.Logical instructions.mp4 56.5 MB
7.Pipelining/27.Gate 2014.mp4 55.6 MB
4.Machine instructions and Addressing modes/9.Base register mode.mp4 55.4 MB
7.Pipelining/19.Delayed Branching.mp4 55.3 MB
7.Pipelining/10.Structural dependency - 1.mp4 54.9 MB
1.Cache/11.Problems on set associative mapping -- 2.mkv 53.8 MB
4.Machine instructions and Addressing modes/16.Arithmetic instructions.mp4 52.5 MB
4.Machine instructions and Addressing modes/4.Implied and Immediate mode.m4v 51.3 MB
4.Machine instructions and Addressing modes/7.Relative addressing mode.mp4 51.2 MB
2.Memory Interfacing/8.Example 2.mp4 49.9 MB
6.IO interface/2.Isolated vs memory mapped IO.m4v 49.3 MB
2.Memory Interfacing/4.3 Level Memory.mp4 48.3 MB
5.ALU Data path and Control Unit/6.Instruction decoder.mp4 47.4 MB
1.Cache/6.Disadvantage of Direct mapping.mkv 47.2 MB
4.Machine instructions and Addressing modes/22.Conditional branches.mp4 46.9 MB
1.Cache/14.Gate 2013 question on Set Associative Mapping.m4v 46.9 MB
2.Memory Interfacing/9.Example 3.mp4 45.1 MB
7.Pipelining/3.Gate 99 question.m4v 45.0 MB
1.Cache/4.Direct mapping problems 2.mkv 44.3 MB
1.Cache/7.Introduction to associative mapping.mkv 44.2 MB
5.ALU Data path and Control Unit/15.Execute phase of register reference instructions-5.mp4 44.1 MB
2.Memory Interfacing/16.Memory Interleaving.mp4 43.7 MB
7.Pipelining/4.GATE 2009 question.mp4 43.4 MB
2.Memory Interfacing/20.Gate 2016 question on memory hiraechy.mp4 43.3 MB
3.Secondary Memory/1.Introduction.m4v 43.2 MB
6.IO interface/3.Serial vs parallel transmission Page.m4v 42.8 MB
3.Secondary Memory/9.Example 7.mp4 42.6 MB
1.Cache/15.Gate 2014 question on Hit Ratio.mp4 42.3 MB
5.ALU Data path and Control Unit/20.Hardwired control unit ex - 2.mp4 41.1 MB
7.Pipelining/20.GATE 2008 question.mp4 40.8 MB
1.Cache/9.Set associative mapping.mkv 40.3 MB
5.ALU Data path and Control Unit/7.Instruction cycle.mp4 39.8 MB
4.Machine instructions and Addressing modes/6.Direct and indirect mode.mp4 39.3 MB
2.Memory Interfacing/2.Memory Hierarchy.m4v 38.4 MB
1.Cache/12.Comparing all the mappings.mkv 37.9 MB
2.Memory Interfacing/1.Introduction.m4v 37.8 MB
2.Memory Interfacing/17.Gate Question on memory Interleaving.mp4 37.3 MB
6.IO interface/12.Gate question 1.mp4 36.4 MB
7.Pipelining/26.GATE 11 question.mp4 35.8 MB
7.Pipelining/24.Register renaming.mp4 35.1 MB
7.Pipelining/6.Gate 04 question.mp4 34.5 MB
2.Memory Interfacing/15.Methods to avoid cache coherence problem.mp4 33.3 MB
2.Memory Interfacing/18.Gate 2006 on memory Interleaving.mp4 33.0 MB
1.Cache/22.Gate 2014 question on Doubling the Association.mp4 32.9 MB
3.Secondary Memory/4.Example 3.mp4 31.5 MB
2.Memory Interfacing/12.Example 6.mp4 31.4 MB
6.IO interface/15.Gate question 4.mp4 30.8 MB
7.Pipelining/8.GATE 2015 question.mp4 29.2 MB
5.ALU Data path and Control Unit/23.Difference between hardwired and microprogrammed CU.mp4 28.8 MB
4.Machine instructions and Addressing modes/14.Types of instructions.mp4 27.9 MB
4.Machine instructions and Addressing modes/12.Gate 2004.mp4 27.7 MB
4.Machine instructions and Addressing modes/15.Data transfer instructions.mp4 27.7 MB
1.Cache/20.Gate 2012 question.mp4 27.7 MB
2.Memory Interfacing/11.Example 5.mp4 26.9 MB
1.Cache/23.Gate 2014 question on Set Associative Mapping.mp4 26.5 MB
2.Memory Interfacing/7.Example 1.mp4 25.5 MB
7.Pipelining/9.Dependencies.mp4 25.5 MB
5.ALU Data path and Control Unit/24.GATE 2004 question on microprogramming.mp4 24.9 MB
1.Cache/19.Gate 2011 question on Tag directory.mp4 24.8 MB
3.Secondary Memory/6.Example 5.mp4 24.5 MB
2.Memory Interfacing/21.Gate 2016 question on set associative mapping.mp4 24.3 MB
2.Memory Interfacing/6.Cache replacement algorithms.mp4 24.2 MB
4.Machine instructions and Addressing modes/8.Indexed addressing mode.mp4 24.1 MB
6.IO interface/17.Gate question 6.mp4 23.9 MB
1.Cache/16.Gate 1990 question on Set Associative Mapping.mp4 23.8 MB
3.Secondary Memory/5.Example 4.mp4 23.2 MB
4.Machine instructions and Addressing modes/11.Gate 2002.mp4 22.1 MB
6.IO interface/16.Gate question 5.mp4 21.9 MB
7.Pipelining/7.GATE 2014 question.mp4 21.3 MB
2.Memory Interfacing/5.Example 1.mp4 20.9 MB
7.Pipelining/2.Gate 2000 question.m4v 19.1 MB
2.Memory Interfacing/22.Gate 2014 Question on memory hierarchy.mp4 18.4 MB
3.Secondary Memory/2.Example 1.m4v 18.3 MB
3.Secondary Memory/8.Example 6.mp4 18.2 MB
2.Memory Interfacing/26.Gate 2006 on Memory hierarchy.m4v 17.6 MB
1.Cache/17.Gate 2005 question on Direct Mapping.mp4 15.4 MB
2.Memory Interfacing/14.Cache coherence problem.mp4 15.1 MB
3.Secondary Memory/3.Example 2.mp4 15.1 MB
6.IO interface/13.Gate question 2.mp4 14.5 MB
4.Machine instructions and Addressing modes/10.Gate 2000.mp4 12.0 MB
2.Memory Interfacing/25.Gate 2004 on Memory hierarchy.mp4 10.7 MB
4.Machine instructions and Addressing modes/13.Gate 2001.mp4 8.0 MB
2.Memory Interfacing/23.Gate 2015 on memory hieraechy.mp4 7.6 MB
2.Memory Interfacing/19.Gate 2016 on memory hierarchy.mp4 7.4 MB
8.Practice Questions/7.Practice Questions and Solutions Set-7.pdf 366.8 KB
8.Practice Questions/8.Practice Questions and Solutions Set-8.pdf 269.1 KB
8.Practice Questions/1.Practice Questions and Solutions Set-1.pdf 164.6 KB
8.Practice Questions/5.Practice Questions and Solutions Set-5.pdf 154.8 KB
8.Practice Questions/4.Practice Questions and Solutions Set-4.pdf 121.4 KB
8.Practice Questions/2.Practice Questions and Solutions Set-2.pdf 86.0 KB
8.Practice Questions/6.Practice Questions and Solutions Set-6.pdf 79.8 KB
8.Practice Questions/3.Practice Questions and Solutions Set-3.pdf 78.6 KB
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RavindraBabu Ravula - GATE - 2021 - Computer Organization and Architecture - CoursesGhar

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